./cad/covered, Verilog code coverage analyzer (stable release version)

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Branch: pkgsrc-2015Q1, Version: 0.4.7nb5, Package name: covered-0.4.7nb5, Maintainer: dmcmahill

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is for a stable release version.
There is a separate package (covered-current) which is made of
development snapshots.


Required to run:
[lang/tcl] [cad/verilog]

Required to build:
[devel/gperf]

Master sites:

SHA1: 9dd9da4d739db15e5e2ea36f2767136a825a4728
RMD160: 63720610a24e6e71b9622586d561e3eb92a606f5
Filesize: 1052.648 KB

Version history: (Expand)