./cad/covered, Verilog code coverage analyzer (stable release version)

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Branch: CURRENT, Version: 0.7.10nb3, Package name: covered-0.7.10nb3, Maintainer: dmcmahill

Covered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.

Please note that this package is for a stable release version.
There is a separate package (covered-current) which is made of
development snapshots.

Required to run:
[lang/tcl] [x11/tk] [cad/iverilog]

Required to build:
[pkgtools/x11-links] [devel/gperf] [x11/xorgproto]

Master sites:

Filesize: 3035.413 KB

Version history: (Expand)

CVS history: (Expand)

   2023-01-29 22:18:34 by Ryo ONODERA | Files touched by this commit (2527)
Log message:
*: Recursive revbup from graphics/freetype2
   2021-10-26 12:04:17 by Nia Alarie | Files touched by this commit (63)
Log message:
cad: Replace RMD160 checksums with BLAKE2s checksums

All checksums have been double-checked against existing RMD160 and
SHA512 hashes
   2021-10-07 15:20:33 by Nia Alarie | Files touched by this commit (63)
Log message:
cad: Remove SHA1 hashes for distfiles
   2020-08-17 22:20:41 by Leonardo Taccari | Files touched by this commit (2202)
Log message:
*: revbump after fontconfig bl3 changes (libuuid removal)
   2020-01-26 06:26:29 by Roland Illig | Files touched by this commit (189)
Log message:
all: migrate some SourceForge homepage URLs back from https to http


In the above commit, the homepage URLs were migrated from http to https,
assuming that SourceForge would use the same host names for both http and
https connections. This assumption was wrong. Their documentation at
https://sourceforge.net/p/forge/documentation/Custom%20VHOSTs/ states
that the https URLs use the domain sourceforge.io instead.

To make the homepages from the above commit reachable again, pkglint has
been extended to check for reachable homepages. This check is only
enabled when the --network command line option is given.

Each of the homepages that referred to https://$project.sourceforge.net
before was migrated to https://$project.sourceforge.io (27), and if that
was not reachable, to the fallback URL http://$project.sourceforge.net
   2020-01-19 00:36:14 by Roland Illig | Files touched by this commit (3046)
Log message:
all: migrate several HOMEPAGEs to https

pkglint --only "https instead of http" -r -F

With manual adjustments afterwards since pkglint 19.4.4 fixed a few
indentations in unrelated lines.

This mainly affects projects hosted at SourceForce, as well as
freedesktop.org, CTAN and GNU.
   2018-03-12 12:18:01 by Thomas Klausner | Files touched by this commit (2155)
Log message:
Recursive bumps for fontconfig and libzip dependency changes.
   2016-10-09 01:12:23 by Kamil Rytarowski | Files touched by this commit (1) | Package updated
Log message:
Switch from cad/verilog to cad/iverilog

No PKGREVISION bump as it was update as while ago.