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NOTICE: This package has been removed from pkgsrc./
cad/covered-current,
Verilog code coverage analyzer (development snapshot)
Branch: CURRENT,
Version: 20060904nb5,
Package name: covered-current-20060904nb5,
Maintainer: dmcmahillCovered is a Verilog code coverage analysis tool that can be useful
for determining how well a diagnostic test suite is covering the
design under test. Typically in the design verification work flow, a
design verification engineer will develop a self-checking test suite
to verify design elements/functions specified by a design's
specification document. When the test suite contains all of the tests
required by the design specification, the test writer may be asking
him/herself, "How much logic in the design is actually being
exercised?", "Does my test suite cover all of the logic under test?",
and "Am I done writing tests for the logic?". When the design
verification gets to this point, it is often useful to get some
metrics for determining logic coverage. This is where a code coverage
utility, such as Covered, is very useful.
Please note that this package is a development snapshot and while it
contains the latest and greatest features, it may be buggy as well.
There is a separate package which is made of the stable releases.
Required to run:[
cad/verilog] [
lang/tcl] [
x11/tk]
Required to build:[
pkgtools/x11-links] [
devel/gperf] [
x11/renderproto]
Master sites:
SHA1: 78869b20bc6e032b4dac3a3029c4ea6a97962d3a
RMD160: c1a9e841f7e0a341bd8bce5c4f04e349e0b07672
Filesize: 1512.83 KB
Version history: (Expand)
- (2016-10-09) Package deleted from pkgsrc
- (2014-01-11) Updated to version: covered-current-20060904nb5
- (2013-06-06) Updated to version: covered-current-20060904nb4
- (2013-06-05) Updated to version: covered-current-20060904nb3
- (2013-06-03) Updated to version: covered-current-20060904nb2
- (2012-08-22) Updated to version: covered-current-20060904nb1
CVS history: (Expand)