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./wip/py-verilog, Python-based Hardware Design Processing Toolkit for Verilog HDL

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Branch: CURRENT, Version: 1.0.6, Package name: py312-verilog-1.0.6, Maintainer: jihbed.research

Required to run:
[devel/py-setuptools] [textproc/py-jinja2] [lang/python37]

Required to build:
[pkgtools/cwrappers]

Master sites:

https://files.pythonhosted.org/packages/source/p/pyverilog/ (Download)

RMD160: 4bfb304e822d4b188a072e8192ee190b309a0f8b
Filesize: 157.104 KB

Version history: (Expand)

(2024-09-19) Updated to version: py312-verilog-1.0.6
(2024-09-19) Package has been reborn
(2024-09-15) Package deleted from pkgsrc
(2023-02-13) Package has been reborn
(2023-02-13) Updated to version: py310-verilog-1.0.6
(2021-10-08) Updated to version: py39-verilog-1.0.6